1. Field
Embodiments of the present invention relate to semiconductor devices.
2. Description of Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted on a substrate in a stacked configuration. An edge view of a conventional semiconductor package 20 (without molding compound) is shown in prior art FIGS. 1 and 2. Typical packages include a plurality of semiconductor die 22, 24 mounted to a substrate 26. Although not shown in FIGS. 1 and 2, the semiconductor die are formed with die bond pads on an upper surface of the die. Substrate 26 may be formed of an electrically insulating core sandwiched between upper and lower conductive layers. The upper and/or lower conductive layers may be etched to form conductance patterns including electrical leads and contact pads. Wire bonds are soldered between the die bond pads of the semiconductor die 22, 24 and the contact pads of the substrate 26 to electrically connect the semiconductor die to the substrate. The electrical leads on the substrate in turn provide an electrical path between the die and a host device. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.
It is known to layer semiconductor die on top of each other either with an offset (prior art FIG. 1) or in a stacked configuration (prior art FIG. 2). In the offset configuration of FIG. 1, the die are stacked with an offset so that the bond pads of the next lower die are left exposed. The offset requires a greater footprint on the substrate, where space is at a premium. In the stacked configuration of FIG. 2, two or more semiconductor die are stacked directly on top of each other, thereby taking up less footprint on the substrate as compared to an offset configuration. However, in a stacked configuration, space must be provided between adjacent semiconductor die for the bond wires 30. In addition to the height of the bond wires 30 themselves, additional space must be left above the bond wires, as contact of the bond wires 30 of one die with the next die above may result in an electrical short. As shown in FIG. 2, it is therefore known to provide a dielectric spacer layer 34 to provide enough room for the bond wires 30 to be bonded to the die bond pad on the lower die 24.
Once die are diced from a wafer, individual die are picked and placed onto respective positions on a panel of substrates, atop a layer of uncured die-attach adhesive. Prior to die attach at a given substrate location, visual inspection is used to align the die with the respective substrate locations. If proper alignment is not detected in a given instance, or some other problem with that substrate location is identified, that substrate location is skipped and the die is placed at the next substrate. FIG. 3 is a prior art view of the first two columns of a substrate panel 40 after die 42 have been tacked onto respective substrate locations 44. As shown, one substrate location 44a has been skipped and did not receive a semiconductor die 42.
When the die are initially placed at substrate locations, the die-attach adhesive is a B-stage adhesive that is tacky to hold the die, but not yet fully cured. The die attach adhesive may be cured in a lamination process, where pressure and heat are applied to the die attach adhesive. Heat is applied to an underside of the substrate by a workstation on which the substrate panel is supported.
Pressure is applied to an upper surface of the die by a lamination head, examples of which are shown in prior art FIGS. 4 and 5. The lamination head 50 is a unitary piece including a row of lamination pads 52. The number of pads 52 in the row may match the number of substrate locations 44 in a column of substrates on panel 40. In the example shown, there are four substrate locations 44 and four lamination pads 52. For example, as shown in prior art FIG. 6, the lamination head 50 needs to be registered in a parallel relation to the work station on which the substrate panel 40 is supported. If this step is skipped or not properly performed, the lamination head may be skewed at an angle with respect to the substrate panel. Given the unitary construction of lamination head 50, when one edge of the lamination head contacts the die at one edge of the substrate panel, the opposite edge of the lamination panel may not properly contact the die at the opposite edge of the substrate panel. As such, the unitary lamination head 50 may exert too much force on the die 42 on one edge of the substrate panel 40, and not enough force on the die 42 on the opposite edge of the substrate panel 40.
Referring now to prior art FIG. 7, it may also happen for various reasons that some die 42 extend higher above the surface of panel 40 than others. For example, in FIG. 7, die 42a is higher than other die 42, and die 42b is lower. In this instance, unitary lamination head 50 will exert more force on die 42a than on other die 42, and less force on die 42b than on other die 42.
Referring now to prior art FIGS. 8 and 9, where each substrate location in a column has received a semiconductor die, the force exerted on each die by the lamination head may be controlled. For example, it may be desired to exert a force F1 of 30 N on each semiconductor die 42. Accordingly, the lamination head may exert an opposite force F2 in this example of 30 N×4=120 N. However, as noted above, it may happen that a substrate location 44a in a column did not receive a semiconductor die 42, as shown in FIG. 9. The lamination head 50 still exerts a downward force of 120 N. However, in this instance, that force is borne by only three semiconductor die 42. As such, the force F3 on each die 42 in the column undesirably increases to 120÷3=40 N.